ယွပ်ႉ၊
လုၵ်ႉတီႈ ၽူႈႁူမ်ႈၼႃႈၵၢၼ်
3D Chiplet Engineer
ၵႃႈၶၼ်ၸွမ်းၼင်ႇယွၼ်း
ႁူဝ်ယွႆႈ
- မဵဝ်းၵၢၼ်ငၢၼ်း
- ၸူဝ်ႈၶၢဝ်း
- ရီႇမွတ်ႇ
- ၸႂ်ႈၶႃႈ
- ၶွမ်ႊပၼီႊ
- Vertical Compute
ၶေႃႈသပ်းလႅင်း
About Us : AI compute is hitting a hard physical wall, and memory bottlenecks are throttling the entire industry. Founded in October 2024 and backed by €57M in funding, Vertical Compute is solving this with proprietary Vertical Integrated Memory (VIM™) chiplets, making AI hardware faster, greener, and vastly more scalable. We are an interdisciplinary team transforming breakthrough semiconductor physics into commercial reality.
Why Now : After 18 months of intensive R&D, Vertical Compute has reached a critical inflection point. Our underlying technology is validated, and we have successfully met our core technical milestones. Armed with a proven technical data package and ongoing system studies, we are now shifting from pure R&D to active engagement with global enterprise customers. As we prepare for our next phase of scale and growth starting in 2027, joining us today means taking direct ownership of the hardware foundation that will power the next era of AI compute.
About the role:
We are looking for a 3D Integration / Chiplet Expert to define and implement 2.5D/3D advanced packaging solutions for our Vertical Integrated Memory (VIM) technology. You will collaborate across teams to define optimal interconnect strategies and die stacking approaches to enable high-bandwidth, low-power operation. This job sits at the intersection of SoC architecture (specifically the physical design) , package design, and 3D manufacturing processes.
Key Responsibilities:
• Integration Architecture & Process Definition :
Develop and define architectures for 2.5D/3D stacking of VIM chiplets with compute chiplets.
Collaborate with design and technology teams to develop interconnect solutions that ensure high bandwidth and low latency.
Define clearly the impact of the chiplet physical design chiplets (through-silicon vias, micro-bumps, hybrid bonds, redistribution layers, and chiplet interfaces, …)
define fabrication flows and design rules with foundries, packaging partners, and internal physical design teams
• Performance Analysis & Simulation:
Conduct early multi-physics simulations (thermal, electrical, mechanical) to analyze and optimize the performance and reliability of integrated systems.
drive external partners for final package design
• Collaboration & Communication:
Partner closely with design, process engineering, metrology, and system architecture teams.
Participate in conferences, standardization bodies and industry events to promote or lead discussions about the future of chiplet integration.
• Technical Leadership:Provide
technical leadership and project management guidance to multidisciplinary teams.
About the team:
This role is part of the Product & system team, partnering closely with our cross-functional engineering teams in Product & system and Memory Design. We foster a highly collaborative, inclusive environment where strong alignment, high transparency and seamless team coordination are central to our shared success.
About who you are:
• You’ve spent 5–10 years exploring the frontiers of 2.5D/3D packaging and heterogeneous integration, turning complex ideas into manufacturable systems.
• You have a deep understanding on the SoC physical design, TSVs, Redistribution Layers, hybrid bonding and how they are used at system level to implement chip IOs (Functional and power IOs)
• You are mastering Integrity 3D-IC Platform to define the chiplets interface, to define 3D stacking system, to generate the 3Dblox views, and to run all the 3D system level analysis (Power Delivery Network, Thermal, STA, LVS, SI/PI, …)
• You thrive where architecture meets technology — translating ambitious concepts into elegant, high-performance designs.
• Multi-physics isn’t just theory to you; you use thermal, electrical, and mechanical simulations to see the whole system clearly.
• You’re naturally collaborative — just as comfortable in technical deep dives as you are building bridges between design, process, and system teams.
• You’re the kind of engineer who balances vision with execution: leading projects, mentoring peers, and pushing boundaries with a calm hand.
• Above all, you’re curious — drawn to the challenge of building something new and meaningful at the intersection of memory, compute, and packaging innovation.
• Fluency in English with strong written and verbal communication abilities.
Why Join Us:
• You will get the opportunity to work at the forefront of memory technology innovation.
• Vertical Compute is not only a state-of-the art but also a human adventure. We believe you must have a lot of fun developing the best of you. Making sure you and your team are going to enjoy the journey and become passionate about what we do is a key goal of our founders.
• You can be part of a talented and dedicated team in a fast-paced startup environment.
• In this role, you contribute to projects that will have a significant impact on the future of computing and electronics.
• You can count on a motivating total rewards package.
• Flexible ways of working.
Join us in shaping the future of compute & memory technology — and celebrating success!
Find Jobs in France on Arbeitnow
Source: Arbeitnow (https://www.arbeitnow.fr/jobs/companies/vertical-compute/remote-3d-chiplet-engineer-grenoble-90023)
Why Now : After 18 months of intensive R&D, Vertical Compute has reached a critical inflection point. Our underlying technology is validated, and we have successfully met our core technical milestones. Armed with a proven technical data package and ongoing system studies, we are now shifting from pure R&D to active engagement with global enterprise customers. As we prepare for our next phase of scale and growth starting in 2027, joining us today means taking direct ownership of the hardware foundation that will power the next era of AI compute.
About the role:
We are looking for a 3D Integration / Chiplet Expert to define and implement 2.5D/3D advanced packaging solutions for our Vertical Integrated Memory (VIM) technology. You will collaborate across teams to define optimal interconnect strategies and die stacking approaches to enable high-bandwidth, low-power operation. This job sits at the intersection of SoC architecture (specifically the physical design) , package design, and 3D manufacturing processes.
Key Responsibilities:
• Integration Architecture & Process Definition :
Develop and define architectures for 2.5D/3D stacking of VIM chiplets with compute chiplets.
Collaborate with design and technology teams to develop interconnect solutions that ensure high bandwidth and low latency.
Define clearly the impact of the chiplet physical design chiplets (through-silicon vias, micro-bumps, hybrid bonds, redistribution layers, and chiplet interfaces, …)
define fabrication flows and design rules with foundries, packaging partners, and internal physical design teams
• Performance Analysis & Simulation:
Conduct early multi-physics simulations (thermal, electrical, mechanical) to analyze and optimize the performance and reliability of integrated systems.
drive external partners for final package design
• Collaboration & Communication:
Partner closely with design, process engineering, metrology, and system architecture teams.
Participate in conferences, standardization bodies and industry events to promote or lead discussions about the future of chiplet integration.
• Technical Leadership:Provide
technical leadership and project management guidance to multidisciplinary teams.
About the team:
This role is part of the Product & system team, partnering closely with our cross-functional engineering teams in Product & system and Memory Design. We foster a highly collaborative, inclusive environment where strong alignment, high transparency and seamless team coordination are central to our shared success.
About who you are:
• You’ve spent 5–10 years exploring the frontiers of 2.5D/3D packaging and heterogeneous integration, turning complex ideas into manufacturable systems.
• You have a deep understanding on the SoC physical design, TSVs, Redistribution Layers, hybrid bonding and how they are used at system level to implement chip IOs (Functional and power IOs)
• You are mastering Integrity 3D-IC Platform to define the chiplets interface, to define 3D stacking system, to generate the 3Dblox views, and to run all the 3D system level analysis (Power Delivery Network, Thermal, STA, LVS, SI/PI, …)
• You thrive where architecture meets technology — translating ambitious concepts into elegant, high-performance designs.
• Multi-physics isn’t just theory to you; you use thermal, electrical, and mechanical simulations to see the whole system clearly.
• You’re naturally collaborative — just as comfortable in technical deep dives as you are building bridges between design, process, and system teams.
• You’re the kind of engineer who balances vision with execution: leading projects, mentoring peers, and pushing boundaries with a calm hand.
• Above all, you’re curious — drawn to the challenge of building something new and meaningful at the intersection of memory, compute, and packaging innovation.
• Fluency in English with strong written and verbal communication abilities.
Why Join Us:
• You will get the opportunity to work at the forefront of memory technology innovation.
• Vertical Compute is not only a state-of-the art but also a human adventure. We believe you must have a lot of fun developing the best of you. Making sure you and your team are going to enjoy the journey and become passionate about what we do is a key goal of our founders.
• You can be part of a talented and dedicated team in a fast-paced startup environment.
• In this role, you contribute to projects that will have a significant impact on the future of computing and electronics.
• You can count on a motivating total rewards package.
• Flexible ways of working.
Join us in shaping the future of compute & memory technology — and celebrating success!
Find Jobs in France on Arbeitnow
Source: Arbeitnow (https://www.arbeitnow.fr/jobs/companies/vertical-compute/remote-3d-chiplet-engineer-grenoble-90023)
သဵၼ်ႈမၢႆၼႆႉ လုၵ်ႉတီႈ ၽူႈႁူမ်ႈၼႃႈၵၢၼ် မႃး။ တၢင်ႇယွၼ်းတီႈဝႅပ်ႉသၢႆႉ ဢၼ်ပဵၼ်ငဝ်ႈငႃႇ။
ၶေႃႈမုလ်း: Vertical Compute
သဵၼ်ႈမၢႆ ဢၼ် Vertical Compute ပၼ်ဝႆႉ။
